1. Field of the Invention
This invention relates to a semiconductor memory device and, more particularly, to an on-chip error detection and correction system adaptable for use therein.
2. Description of the Related Art
Electrically rewritable nonvolatile semiconductor memory devices, i.e., flash memories, increase in error rate with an increase in number of data rewrite operations. In particular, the quest for larger storage capacity and further enhanced miniaturization results in an increase in error rate. In view of this, an attempt is made to mount or “embed” a built-in error correcting code (ECC) circuit on flash memory chips or, alternatively, in memory controllers for control of these chips. An exemplary device using this technique is disclosed, for example, in JP-A-2000-173289.
A host device side using more than one flash memory is designable to have an ECC system which detects and corrects errors occurring in the flash memory. In this case, however, the host device increases in its workload when the error rate increases. For example, it is known that a two-bit error correctable ECC system becomes greater in calculation scale, as suggested by JP-A-2004-152300.
Accordingly, in order to cope with such error rate increase while suppressing the load increase of the host device, it is desired to build a 2-bit error correctable ECC system in the flash memory. What is needed in this case is to meet the conflicting requirements: i.e., increasing the ECC system's arithmetic operation speed, and yet lessening possible penalties of read/write speed reduction of the flash memory.